Падарян В. А. - Архитектура ЭВМ и язык ассемблера - Лекция 21

Description:

In this lecture, the instructor covers the organization of buses, typical connections between the CPU and RAM, the bus from a hardware developer's perspective, bus characteristics, examples of buses, synchronization of memory accesses, and further examples of buses. 0:00:19 – Organization of buses; 0:04:42 – Typical connection between CPU and RAM; 0:38:22 – Bus from a hardware developer's perspective; 0:41:12 – Bus characteristics; 0:55:57 – Examples of buses (1); 0:59:14 – Synchronization of memory accesses; 1:16:13 – Examples of buses (2).